This invention relates to commputer systems and, more particularly, to an interface circuit for the orderly transfer of control information transmitted along a bus coupling several peripheral units and the central control unit of the computer system.
A computer system bus constitutes a set of communication lines disposed for coupling information among various units of the system. Control over the bus normally resides with the control unit, which is part of a central processing unit (CPU). Oftentimes, however, control of the bus must be transfered to a unit peripheral to the central control unit so that particular operations may be performed. An example of an operation requiring control of the bus by a peripheral unit is direct memory access by which data are transferred to or from the system's memory, or from the system's memory to the outside world or the reverse, without having the data move through the CPU.
Various circuit arrangements are used to allow the transfer of bus control between the central control unit and its various peripheral devices. One such arrangement found in microcomputer systems is shown in FIG. 1, which has a CPU 10 connected with a plurality of peripheral units, shown as blocks 14, 15, and 16 by lines 11,12 and 13. The continuation of the lines 11 and 12 by broken lines to the right indicate more peripheral units may be connected in a similar manner to the CPU 10.
These peripheral units can be an entire subsystem, such as a magnetic tape unit which could be used to store information in a computer system. However, as used herein, the term "peripheral unit" refers to that part of the subsystem which communicates directly with the CPU 10. In a microcomputer system the peripheral unit as defined is typically in the form of a single integrated circuit device.
Each peripheral unit is connected in parallel to the CPU 10 by a bus request line 11 with a branch line 13. The term BUSREQ will sometimes hereinafter refer to the signal transmitted on the bus request line 11. Arrows on the branch line 13 indicate that signals on the bus request lines 11 and 13 are bidirectional, i.e., signals pass from the central control unit of the CPU 10 to each peripheral unit 14, 15, and 16 and pass from the peripheral units back to the central control unit.
The peripheral units of the system are also connected in series to the central control unit by a bus acknowledgment line 12. The term BUSACK will sometimes hereinafter refer to the signal transmitted on the line 12. Each peripheral unit is connected to the line 12 by a bus acknowledgment input terminal 51 and a bus acknowledgment output terminal 52. The terms BAI and BAO will sometimes hereinafter refer to the terminals 51 and 52, respectively. Arrows on the bus acknowledgment line 12 indicate that BUSACK signals from the central control unit of the CPU 10 enter the peripheral unit through the BAI input terminal 51 and are relayed to a succeeding peripheral unit by the BAO output terminal 52. For example, the BAO ouput terminal 52 of the preceding peripheral unit 14 transmits a BUSACK signal to the peripheral unit 15 which receives the signal on the line 12 through its input terminal 51.
A peripheral unit requests control of the bus (not shown) by transmitting a BUSREQ signal from its bus request terminal 50 (BUSREQ) through its branch line 13 onto the main bus request line 11 to the CPU 10. The CPU monitors the bus request line 11 and grants the use of the bus at an appropriate time to the requesting device. Such granting of bus control is indicated by sending an acknowledgement signal (BUSACK) from the CPU 10 to the serially connected peripheral devices along the bus acknowledgment line 12. If there is only one peripheral device in the system, then that device will receive the acknowledgement signal through its BAI input terminal 51. The peripheral unit will then take control of the bus. When the peripheral unit has completed its use of the bus, it stops driving the bus request line 11. The central control unit of the CPU 10 senses this condition, resumes control of the bus and indicates this by removing its BUSACK signal on the line 12 to the peripheral unit.
For a system with more than one peripheral unit, this arrangement in FIG. 1 establishes a priority based upon the proximity of the peripheral unit to the CPU 10. Each peripheral unit is set so that it will not transfer a BUSACK signal if the unit is the one requesting control of the bus. For example, the peripheral unit 14 has the highest priority over the remaining peripheral units. It is the first to receive the bus acknowledgment signal from the CPU 10 and it wil block the bus acknowledgment signal from going to the peripherial unit 15 if the peripheral unit 14 is requesting bus control. The unit 14 thus has the first chance of bus control. If the unit 14 is not the unit requesting bus control, it allows the bus acknowledgment signal on the line 12 to pass to the next peripheral unit. The bus acknowledgment signal continues to succeeding peripheral units until the unit requesting bus control is reached. In this manner the connections of the peripheral units establish priority in the bus control protocol.
In cases where two (or more) units have made a simultaneous request for control of the bus, the nearer unit (the device closer to the CPU 10) gains control first and blocks the bus acknowledgment signal propagation to the subsequent units. When the first unit is through, it allows the bus acknowledgment signal to travel to the succeeding units until the bus acknowledgment signal is received by the second requesting peripheral unit. At this point the second unit gains control of the bus. When all of such units which requested the bus have completed their operations, the BUSREQ signal on the lines 11 and 13 is removed. The CPU 10 senses this change in signal status, removes the BUSACK signal and regains control of the bus.
Such a bus protocol arrangement has certain shortcomings. One such shortcoming occurs when one particular peripheral unit has control of the bus. That is, the unit has a signal on the bus request lines 11, 13 and the CPU 10 has generated a BUSACK signal. All of the peripheral units preceding the unit with bus control are in receipt of the BUSACK signal, while the controlling peripheral unit blocks the signal from subsequent peripheral units. When the unit in control completes its operation, it stops sending its BUSREQ signal, thus removing the signal on the bus request lines 11, 13. This same unit will also transmit the BUSACK signal originating in the CPU 10 to the subsequent peripheral units. By operation of the CPU 10, which is synchronized with a clock, the BUSACK signal will usually be removed one clock period after the BUSREQ signal removal has been sensed. However, a problem will arise if, during that interval, another unit requests the bus. This second unit will then send a BUSREQ signal and will also be in receipt of a BUSACK signal thereby allowing it to assume bus control. But within one clock period the CPU 10 will remove the BUSACK signal and assert control of the bus. Thus, a conflict between the CPU 10 and the second requesting device might occur.
A seemingly simple solution to this problem is to require that the peripheral units generate a BUSREQ only after two or more clock periods have elapsed following completion of a bus request by the first peripheral unit. Such a simple solution, however, means that all the peripheral units must receive the CPU clock signals. An extra signal line to the peripheral units is required and, if the peripheral unit is manufactured in the form of an integrated circuit, another pin for the integrated circuit package is required. This solution is not desirable and is sometimes impractical.
Typically, in most microcomputer systems the CPU and peripheral units are manufactured in MOS technology. This means that the current handling ability of such highly integrated MOS transistor devices is limited. On the other hand, large currents are desirable for driving the signals on the lines connecting the various units of the computer system, such as the bus request line 11, 13 in FIG. 1. In an actual system, these lines would be spread over several printed circuit boards resulting in large capacitances; and, large currents are required to quickly change the voltage levels on these lines.
In the computer system shown in FIG. 1, the bus acknowledgment line 12 does not usually have this shortcoming since the line 12 is broken into short segments between peripheral units. Each segment has a small capacitance in contrast to the large capacitance of the bus request line with its long main line 11 and many branches 13.
A solution to this problem is to install bipolar buffer drivers at the bus request terminal of each peripheral unit as shown in FIG. 2. This solution is unsatisfactory, however, because the bus request terminal of each peripheral unit must have both input sensing and output driving capabilities for proper functioning of the bus request protocol. The particular peripheral unit must be able to sense when another peripheral unit is making a bus request signal. This bidirectional operation is not possible with the bipolar buffer drivers. To get around this, it is possible to make another bus terminal for each peripheral unit which will receive the BUSREQ signal directly from the line 11. However, this further complicates the arrangement and requires another pin for each peripheral unit.